Voltage regulators are commonly used in power management systems of PC motherboards, laptop computers, mobile phones and many other products. In these systems, the regulator design is required to operate in conjunction with a widely varying load impedance, while maintaining a high PSRR (“Power Supply Rejection Ratio”). For example, in a mobile phone, a voltage regulator usually provides power supply for several devices. Those devices can be enabled independently. Thus, the load of the regulator varies. The voltage regulator should provide stable voltage supply for these devices under different load conditions. In addition, to provide a clean voltage supply to the devices, the voltage regulator also needs to suppress voltage disturbances from its unregulated supply (batteries, switching regulators, and other unregulated voltage sources). This application requires a high PSRR voltage regulator circuit. What is desired, therefore, is a voltage regulator design with high PSRR and high stability under variable load conditions. The present invention is targeted to solve these problems.
A conventional voltage regulator 100 is illustrated in FIG. 1. The conventional linear regulator 100 includes an amplifier 102, a driver transistor PSW, and a resistor divider R1 and R2 coupled between the drain of PSW and ground. The center tap of the resistor divider is fed back to the negative input of the amplifier 102. The positive input of the amplifier 102 receives a reference voltage as is known in the art. The VDD power supply voltage in FIG. 1 is the unregulated input voltage and the VOUT terminal at the drain of transistor PSW is the regulated output voltage. An exemplary load is shown in FIG. 1, including a load capacitor CL and the Equivalent Series Resistor (R_ESR), and the desired load 104. The capacitor Cpar is the parasitic capacitance at the gate of transistor PSW.
The conventional voltage regulator 100 shown in FIG. 1 has a problem in that it is prone to instability. The load impedance 104 of the regulator 100 can introduce a pole into the transfer function of the circuitry. This load pole varies greatly when the load condition changes. If the load impedance 104 varies over too great a range, an unstable feedback loop may be incurred.
To solve the instability issue, a voltage regulator as disclosed in U.S. Pat. No. 6,300,749 provides within the circuit response a zero capable of moving according to the load variations in load 206. As shown in FIG. 2, compensated voltage regulator 200 introduces a delay phase network (capacitor Cc and resistor Rc) between an operational transconductance amplifier 202 and a buffer amplifier 204, which introduces a zero and a pole to the circuitry. The zero of the regulator is movable to compensate the effect of the variable second pole in the loop gain.
The voltage regulator 200 shown in FIG. 2 provides a compensation network with a moving zero to compensate the variable load pole. However, because the pass transistor PSW usually has a relatively large size, it will introduce a relatively low frequency pole at the gate of the pass transistor. Thus, the regulator 200 needs to either lower the frequency of the dominant pole, or decrease the open-loop dc gain. This approach is limited for those applications needing high PSRR and high bandwidth systems.